When using interrupt, the GIE and TMR0IE bits of the INTCON register should be set.The prescaler rate is set by using the PS2-PS0 bits of the same register. When used, the prescaler should be assigned to the timer/counter by clearing the PSA bit of the OPTION_REG register.Timer mode is selected by the T0CS bit of the OPTION_REG register, (T0CS: 0=timer, 1=counter).In order to use TMR0 properly, it is necessary:

MOVLW b'11110000' SELECT ONLY BITS PSA,PS2,PS1,PS0ĪNDWF OPTION_REG,W CLEAR THEM BY 'LOGIC AND' INSTRUCTION

Likewise, when changing the prescaler assignment from the WDT to TMR0, the following instruction sequence, also written in assembly language, must be executed:.

MOVLW b'11111000' SELECT BITS PS2,PS1,PS0 AND CLEARĪNDWF OPTION_REG,W THEM BY 'LOGIC AND' INSTRUCTION

When changing the prescaler assignment from TMR0 to the watch-dog timer, the following instruction sequence written in assembly language must be executed in order to prevent the microcontroller from reset:īSF OPTION_REG,PSA PRESCALER IS ASSIGNED TO WDT.

The 8-bit prescaler register is not available to the user, which means that it cannot be directly read or written to.

When used as an external clock counter with prescaler, a minimal pulse length or interval between two pulses is only 10nS.

When used as an external clock counter, without prescaler, a minimal pulse length or a delay between two pulses must be 2 Tosc + 20 nS (Tosc is the oscillator clock signal period).

This is why the TMR0 overflow interrupt cannot wake up the processor from Sleep mode. Overflow cannot occur since there are no pulses to count.

When the microcontroller is set in sleep mode, the clock oscillator is turned off.

Accordingly, it is necessary to adjust the value written to the TMR0 register.

Write to the TMR0 register, used as timer, will not cause the pulse counting to start immediately, but with two instruction cycles delay.

When the prescaler is assigned to the watch-dog timer, the CLRWDT instruction will clear both the prescaler and WDT.

When the prescaler is assigned to the timer/counter, any write to the TMR0 register will clear the prescaler.

Additionally it is also worth mentioning: OPTION_REG = 0x0E // Prescaler is assigned to WDT (1:64)Īsm CLRWDT // Assembly command to reset WDT In this example, prescaler (1:64) is assigned to Watch-dog timer. When PSA bit is cleared, prescaler is asigned to TMR0 timer/counter as ilustrated on the figure below: As seen in the table, the same combination of bits gives different prescaler rate for the timer/counter and watch-dog timer, respectively.

Prescaler rate is adjusted by combining these bits.

PS2, PS1, PS0 - Prescaler Rate Select bit.

1 - Prescaler is assigned to the TMR0 timer/counter.

1 - Increment on low-to-high transition on the TMR0 pin.

0 - Increment on high-to-low transition on the TMR0 pin.1 - Timer uses internal cycle clock (Fosc/4).0 - Pulses are brought to TMR0 timer/counter input through the RA4 pin.1 - Interrupt on falling edge of the INT pin (1-0).

0 - Interrupt on rising edge of the INT pin (0-1).1 - PORTB pins can be connected to pull-up resistors.0 - PORTB pull-up resistors are disabled.

Seconds pro timer dow